This application claims the priority of Korean Patent Application No. 2003-70638, filed on Oct. 10, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and more particularly to a recess channel transistor (RCT) used for a highly integrated semiconductor circuit, a method of fabricating the same, and a method of forming a recess channel trench pattern.
2. Description of the Related Art
Lengths of channels are being shortened as a result of high integration density in semiconductor devices such as DRAMs, causing problems such as the short channel effect and punch through between source and drain regions, of which influences are difficult to control. Therefore, recess channel transistors are suggested for increasing the lengths of channels.
In a recess channel transistor, a recess channel trench is formed in an active region defined by a device isolation structure such as a shallow trench isolation (STI). Then, a recess gate that fills the recess channel trench, and source and drain regions that are formed in both sides of the recess gate form the recess channel transistor. Thus, a channel is formed along an outer periphery of the recess channel trench that is much longer than a length of a channel in a planar-type transistor. By doing so, short channel effect is decreased, and punchthrough between the source and drain regions is inhibited.
However, in a conventional method of forming a recess channel trench pattern that forms a recess channel transistor, a pattern of a mask layer (e.g., a photoresist pattern) for forming the recess channel trench is shaped as a straight line. Using the mask layer with the straight-line shaped pattern, a silicon substrate of an active region and an isolating layer of a field region disposed under the mask layer are etched, thereby forming a recess channel trench in the field region as well as in the active region. At this time, an etch selectivity of the silicon substrate to the isolating layer is heightened, so that the depth of the recess channel trench in the field region is less than that formed in the active region.
FIG. 1 is a layout showing a conventional recess channel trench pattern.
Referring to FIG. 1, active regions 22, 24, 26 and 28 that form recess channel transistors are separated by STIs that form field oxide regions 110. Straight-line shaped recess channel trench patterns 12, 14, 16 and 18 are formed across the active regions 22, 24, 26 and 28 and field region 110. The straight-line shaped recess channel trench patterns 12, 14, 16 and 18 are formed by etching the active regions and the field oxide regions.
FIGS. 2A and 2B are sectional views respectively taken along lines A–A′ and B–B′ of FIG. 1.
Referring to FIG. 2A, the STI 110 sloped by a prescribed angle is formed in a silicon substrate 100. Also, recess channel trenches 14 and 16 with a prescribed depth H1 are formed in the silicon substrate 100 that forms the active regions between the STIs 110. As described with reference to FIG. 1, the STI 110 that forms the field region is formed with the recess channel trenches 12 and 18 to a depth H2 that is shallower than the depth H1. The silicon substrate forming the active regions is formed with source and drain regions (not shown). The aforementioned recess channel trenches 12, 14, 16 and 18 are formed by etching the silicon substrate and isolating layer using the mask layer 115 such as a photoresist layer patterned to have the straight line shape as an etch mask.
However, in the recess channel trench with the foregoing sectional structure, the recess channel trench 18 in the field region is apt to intrude into a STI liner 22a that protects the STI as indicated by a dot-lined circle 11 of FIGS. 1 and 2A.
Therefore, a recess gate that is formed later may (electrically) short with the active region through the STI liner 22a. Since a conventional STI structure has a positive slope to secure a gap fill margin of the isolating layer, the liability of causing a short between the recess gate and the active region is further increased in proportion with a depth of the recess channel trench 18 in the field region. Moreover, further decreasing device size causes a reduction in a misalignment margin of the recess channel trench pattern for the purpose of evading the possible short. Even if the recess gate is not actually shorted, mutual interference caused as a result of making the recess channel trench 18 nearer to the substrate material 100 of the active region may bring about an abnormal operation of the recess channel transistor.
Referring to FIG. 2B, in the conventional recess channel trench structure, the active region is formed with the recess channel trench 16 with the depth H1 that is deeper than the prescribed depth H2 formed by etching the field region. The etched amounts are different because the etch selectivity of the silicon substrate material to the isolating layer that forms the STI is large. On the other hand, according to the conventional method of forming the recess channel trench, etching is carried out to form the recess channel trench 16 using the STI 110 with the positive slope as a boundary. Thus, silicon fences 21, or residual substrate areas, are formed on both bottom sides of the recess channel trench 16. That is, as areas 21 indicated by dot-lined circles, the silicon substrate 100 partially remains between the sidewalls of the STI 110 and the recess channel trench 16. If the silicon fences 21 are formed on both bottom sides of the recess channel trench 16 as stated above, the length of the channel around the silicon fence 21 is greatly decreased when forming a recess channel transistor later. Thus, characteristics such as threshold voltage of the transistor are deteriorated.
FIGS. 3A and 3B are sectional views showing a conventional recess channel transistor fabricated using the layout of FIG. 1, taken along lines A–A′ and B–B′ of FIG. 1, respectively.
Referring to FIG. 3A, a recess gate formed by a gate insulating layer 130, a gate polysilicon layer 140a, a gate metal layer 150a, and a capping layer 160a is formed on the recess channel trench 16, thereby forming the recess channel transistor. Referring to FIG. 3A, in the area 11 where the recess channel trench intrudes into the STI liner after the recess gate is formed, a gate conductive layer 180a of the recess gate is shorted with the silicon substrate 100 that forms the active region, which causes malfunction during operation of the transistor.
Referring to FIG. 3B, the length of the channel is shortened between the silicon fences 21 formed on both bottom sides of the recess channel trench (refer to FIG. 2B). Once the length of the channel is shortened between the silicon fences 21, the threshold voltage is decreased, thereby increasing a leakage current.